1. Field of the Invention
The present invention generally relates to a method for processing semiconductor substrates. More specifically, the invention relates to a method for fabricating a gate structure in a semiconductor substrate processing system.
2. Description of the Related Art
The evolution of integrated circuit designs continually requires faster circuitry, greater circuit densities and necessitates a reduction in the dimensions of the integrated circuit components and use of materials that improve electrical performance of such components. Field effect transistors that are used in forming an integrated circuit generally utilize polysilicon gate electrodes deposited upon a gate dielectric that separates the electrode from a channel between the source and drain regions of the transistor. In prior art, high speed transistor structures, the gate dielectric is typically fabricated of a very thin layer of silicon dioxide (SiO2) and/or a very thin layer of one of materials having a high dielectric constant (high K) such as HfO2, Al2O3, ZrO2, barium strontium titanate (BST), lead zirconate titanate (PZT), ZrSiO2, HFSiO2, HfSiON, or TaO2. Herein high K materials are the materials having a dielectric constant greater than 4.0. The polysilicon electrodes in these transistor structures are fabricated using a plasma etching in oxygen-containing chemistry, such as HBr/Cl2/CF4/HeO2, HBr/Cl2/CF4/O2 and the like. Oxygen in these chemistries is used to improve selectivity of the gate dielectric to silicon during the etch.
To form a transistor, regions in the substrate are doped to form source and drain regions. A high K dielectric such as hafnium dioxide is deposited over the substrate. Polysilicon is then deposited over the dielectric layer and the polysilicon is then annealed at a high temnperature. To define the gate electrode, a patterned hard mask layer (typically, SiO2) is formed atop the polysilicon. The polysilicon is etched in a two-step process. The first step comprises a main etch wherein polysilicon is removed until some of the underlying dielectric layer is exposed. The second step comprises an overetch wherein the remaining polysilicon that is not protected by the mask is removed. The main etch uses an aggressive chemistry comprising HBr and Cl2 as main etchant gas. The overetch uses a less aggressive chemistry comprising HBr, Cl2, and O2, where the O2 enhances the selectivity of the etch to SiO2.